The present invention relates to a method of producing a semiconductor device in which an impurity layer is formed through implantation of impurity ions and subsequent annealing.
The trend in manufacturing semiconductor devices is toward smaller, finer, more miniaturized devices. According to a scaling rule in the production of microfine field-effect type semiconductor devices, when reducing the minimum size to 1/L, it is necessary that the depth X.sub.j of junction between the impurity layer and the semiconductor substrate also is reduced to 1/L. To meet such a requirement, attempts have been made to lower the level of energy used in impurity ion implantation and to lower and shorten the temperature and time of annealing.
However, the above-mentioned attempt to lower and shorten the temperature and time of annealing alone cannot well cope with the demand for formation of an impurity layer having a sufficiently small thickness, when the micronization of semiconductor devices proceeds to such an extent as to require the depth X.sub.j meeting the condition of X.sub.j &lt;0.1 .mu.m so that channeling tail of the ion-implanted impurity is not negligible.
When an impurity layer of a depth greater than that X.sub.a of the amorphous layer is formed by ion implantation as shown in FIG. 1A, it is impossible to suppress diffusion of impurities during annealing which is executed for the purpose of activating the ion-implanted impurities, as will be seen from FIG. 1B.
In contrast, when an impurity layer having a depth smaller than the depth X.sub.a of the amorphous layer is formed by ion implantation as shown in FIG. 1C, impurity is prevented from being diffused to a level deeper than the depth X.sub.a during annealing which is executed for the purpose of activating the ion-implanted impurity. Consequently, it is possible to form an impurity layer the depth of which is small enough even after annealing. For these reasons, the conventional semiconductor process employs formation of an amorphous layer prior to the ion implantation which is conducted for the purpose of forming an impurity layer.
It is to be noted, however, dislocation loops 11 appear after the annealing in the vicinity of the interface between the amorphous layer and the crystalline layer, as shown in FIGS. 1B and 1D. Meanwhile, FIG. 6 shows the change in the leak current at the junction between the impurity layer and the Si substrate, as observed when the depth X.sub.a of the amorphous layer is changed while the depth X.sub.j of the impurity layer is maintained constant. As will be understood from FIG. 6, the junction leak current starts to exhibit a remarkable increase when the depth Xa of the amorphous layer has been increased to such an extent that the position of a depletion layer of the junction coincides with the position of the dislocation loops 11.
More specifically, even when the diffusion of impurity to a depth greater than the depth X.sub.a of the amorphous layer is suppressed so as to ensure that the impurity layer has a small depth after the annealing as shown in FIGS. 1C and 1D, the position of the depletion layer and the position of the dislocation loops 11 coincide with each other in this state, thus allowing a large junction leak current to flow. Consequently, it has been impossible to produce microfine semiconductor devices by conventional production methods.